1. Field of the Invention
The present invention relates to a device and method for simulation, and particularly to a testing method and associated simulation device for testing semiconductor integrated circuits such as application-specific integrated circuits (ASIC) that include logic circuits.
2. Description of the Related Art
Logic verification for confirming the correctness of logic circuits is crucial in designing semiconductor integrated circuits such as ASIC. Logic verification methods that use logic simulation have come into widespread use with increases in circuit integration.
Logic simulation is performed by inputting simulation execution control data and descriptions of the logic circuit under design in design language and outputting a resulting time chart that represents the operation. By validating the content of the time chart, designers can confirm the correctness of operation of the logic circuit. Simulation devices for ASIC now in use employ a cyclic simulation test pattern in which expected values are inputted to an LSI tester for each cycle and can verify automatically by comparing expected values with simulation results to determine automatically whether or not simulation results coincide with the designers' expected values.
However, in such prior-art simulation devices for ASIC, tester skew, i.e., the timing difference between a tester's electrical input signals, has not been taken into due consideration, and this tester skew frequently gives rise to the problem that some types of ASIC products may pass simulation tests but then fail tests at the time of shipment.
Referring to FIG. 1, which shows a block diagram of a first simulation device typical of this type of the prior art, such a prior-art simulation device is provided with arithmetic section 6 that reads net list 7, which is circuit connection information, test patterns 8, and library 19 specifying delay times and timing of elements, and performs logic operations and timing verification; and memory section 2 that holds the operation results of arithmetic section 6.
As to the simulation method, i.e., the operation of the prior-art simulation device, referring to FIG. 1, FIG. 2(A) shows one example of a circuit for simulation, and FIG. 2(B) shows a timing chart for the circuit, the object circuit for simulation includes data signal input terminal 13 that inputs data signals of the object process; control signal input terminal 14 that inputs control signals such as clock pulses; data-side combinatory logic 15 that combines data-system signals by a prescribed logic and outputs data signals d; control-side combinatory logic 16 that combines control-system signals by a prescribed logic and outputs control signals c; first-stage sequential circuit element 20 that operates in response to the supply of each of data signals d and control signals c to input terminal D.sub.1 and C.sub.1, respectively, and outputs output signals q from output terminal Q.sub.1 ; and second-stage sequential circuit element 18 that is of the same type as sequential circuit element 20, that operates in response to the supply of each of signals q and control signals c to input terminals D.sub.2 and C.sub.2, respectively, and that outputs output signals qq to an internal circuit from output terminal Q.sub.2.
Even for this type of circuit structure, the simulation method of the prior art converts to a library the timing specifications for operation characteristics that elements should satisfy, which in this case are set-up times (hereinafter referred to as "t.sub.set-up "), uniformly for first-stage sequential circuit element 20 and second-stage sequential circuit element 18, and judges internal timing and output logic with respect to this library.
Referring to FIG. 2(B), set-up time t.sub.set-up is the time interval from the rising edge of a data input signal to data signal input terminals D.sub.1 and D.sub.2 to the rising edge of a control input signal to control signal input terminal C.sub.1 and C.sub.2 for sequential circuit elements 18 and 20, and this time interval is established as a prescribed value .alpha..
This shows that during simulation, these circuits operate correctly if t.sub.set-up .gtoreq..alpha. for both sequential circuit elements 18 and 20, but that there is a possibility for malfunctioning of these circuits if timing t.sub.set-up &lt;.alpha. for both or either of sequential circuit element 18 and 20.
Accordingly, the first simulation method of the prior art allows correct judging of circuit operation for an ideal state in which absolutely no skew occurs in the input signals to data-system input terminal 13 and control-system input terminal 14. This is because judgment of timing is based on the characteristics of the elements for both sequential circuit element 20 of the first stage, which may be affected by tester skew during testing at the time of shipping, as well as for sequential circuit element 18 positioned in a subsequent stage. In a non-ideal case, however, in which skew occurs in input signals to terminals 13 and 14, there is a possibility that, despite satisfactory simulation results, an article will be misjudged as defective at the time of shipping due to a timing relation whereby t.sub.set-up &lt;.alpha..
A second simulation device described in Japanese Patent Laid-open No. 189517/93 is directed toward eliminating the above-described disparity in operation between testers, i.e., circuit malfunctioning due to differences in testers. This second simulation device achieves this object of preventing circuit malfunctioning due to tester differences by determining in advance specific clock signals and data signals, generating an alarm meaning undefined level only for these specific data signals when the timing of these input signals is in a fixed conflict state, and then designing circuits subject to verification such that this undefined level is not generated.
However, this device cannot freely detect conflict states between numerous unspecified clock signals and data signals.
In the above-described first simulation device and method of the prior art, the timing specifications of all sequential circuit elements within a circuit are uniformly defined as specific values that an element should satisfy, and timing or output logic of internal sequential circuit element sections is then judged using this library as a standard. As a result, the first simulation device and method have the drawback that, even for a circuit in which exist many unspecified sequential circuit elements that directly receive the effect of skew between data-system input signals and control-system input signals, timing judgment that takes into consideration the effect of external skew, which properly should be considered with respect to these sequential circuit elements, is not enabled. This inability to exhaustively detect possibilities of circuit malfunctioning due to tester skew arising from the combination of unspecified inputs during testing at the time of shipping results in the drawback that problems in testing at the time of shipping cannot be prevented.
In addition, the second simulation device of the prior art, although directed toward the prevention of circuit malfunctioning due to differences between testers, also suffers from the drawback of limited use because it does not freely detect conflict states between numerous unspecified clock signals and data signals.